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The 74HC138 is a high speed CMOS device.
The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high.
There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3.
The disabled device state results in all outputs being high.
The enable state occurs with E1 and E2 asserted low and E3 asserted high.
The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter